A compact functional verification flow for a RISC-V 321 based core

The structure of a functional verification flow used for the design of a RISC-V core is presented. The paper offers a guide on the test-planning used and details of the flow architecture, showing how to integrate the Universal Verification Methodology with the required, reference models, while implementing key futures in standard verification environments, such as testing regressions and code and structural coverage. The designed flow is compact yet efficient, making it affordable for small design teams, without requiring extra investment other than the already necessary licenses for RTL synthesis and the eventual fabrication of the chip.Agencia Nacional de Investigación e Innovació

A RISC-V based medical implantable SOC for high voltage a current tissue stimulus

A RISC-V based System on Chip (SoC) for high voltage and current tissue stimulus, targeting implantable medical devices, is presented. The circuit is designed in a 0.18μm HV-CMOS process, including the RISC-V 32RVI based microcontroller core, called Siwa —which includes SPI, UART and GPIO interfaces, a packet-based bus and memory controller, and 8kB SRAM—, combined with several biological tissue stimulus and sensing circuits. The complete test chip (analog+RISC-V) occupies a 5mm2 area but only 0.82mm2 correspond to the RISCV micro-controller, which operates up to 20MHz, with average energy needs of less than 48 pJ/cycle (3pJ STD), and for which several reliability and safety issues were considered.Agencia Nacional de Investigación e Innovació

Siwa: A custom RISC-V based system on chip (SOC) for low power medical applications

This work introduces the development of Siwa, a RISC-V RV32I 32-bit based core, intended as a flexible control platform for highly integrated implantable biomedical applications, and implemented on a commercial 0.18 m high voltage (HV) CMOS technology. Simulations show that Siwa can outperform commercial micro-controllers commonly used in the medical industry as control units for implantable devices, with energy requirements below the 50 pJ per clock cycle.Agencia Nacional de Investigación e Innovació

Siwa: a RISC-V RV32I based micro-controller for implantable medical applications

The design of Siwa1, a compact low power custom system on chip (SoC), targeted for implantable/wearable applications, is reported in this paper. Siwa is based on a RISC-V RV32I architecture. It has a centrally controlled non-pipelined structure, and it includes a control interface for an integrated sensing and stimulation device for biological tissues as well as standard communication interfaces. Siwa was developed from scratch using System Verilog, and implemented in a 180nm CMOS technology; Siwa includes a latch based register file c apable to read and write in one clock cycle with an area 30% smaller and a power consumption 25% lower with respect to an equivalent flip flop implementation; also, it has an estimated average power consumption of 70μW (48pJ/cycle) which is comparable to other micro-controllers commonly used in IMD applications.Agencia Nacional de Investigación e Innovació